1. Field of the Invention
The present invention is directed to an output buffer having a compensation capacitor and more particularly, to an output buffer having switches for switching two terminals of a compensation capacitor.
2. Description of Related Art
An output buffer mainly functions as providing a buffering mechanism for impedance matching to a signal terminal and a load terminal. As for the signal terminal, an input terminal of the output buffer provides an input of a quite high input impedance to completely receive a signal outputted from the signal terminal so as to avoid an actuation of the signal inputted from the output buffer. In addition, an output terminal of the output buffer provides an output with low output impedance connected to a load so as to avoid reducing a maximum power that can be outputted by the output buffer due to additional loading effect.
Referring to FIG. 1, FIG. 1 is a structural schematic diagram illustrating an output buffer 100 in the related art. The output buffer 100 includes an input-stage unit 110, an intermediate-stage unit 120, an output-stage unit 130 and a compensation capacitor Cc. The input-stage unit 110 converts a doubled-ended differential input signal Vid to a single-ended differential output signal SS and provides a part of gain. The intermediate-stage unit 120 is used as a buffer and mainly used to compensate a frequency response of a signal to enhance bandwidth of a circuit. Lastly, the compensated signal is transmitted to the output-stage unit 130. The output-stage unit 130 is mainly used to enhance driving ability of the circuit and adequately provide a part of gain.
How the output buffer 100 is operated is described hereinafter. When a status of an input voltage of the input-stage unit 110 is changed, a voltage of an output terminal of the input-stage unit 110 is also changed. When a positive input voltage V1 of the input-stage unit 110 is greater than a negative input voltage V2, an output of a high-state voltage potential is generated in the output terminal of the input-stage unit 110. Otherwise, when the positive input voltage V1 of the input-stage unit 110 is smaller than the negative input voltage V2, an output of a low-state voltage potential is generated in the output terminal of the input-stage unit 110. In addition, an output signal SS of the input-stage unit 110 is transmitted to an input terminal of the intermediate-stage unit 120. The intermediate-stage unit 120 is typically composed of a common-gate (CG) amplifier and mainly configured to provide a low-impedance node to the input-stage unit 110. Thus, a pole generated by the output terminal of the input-stage unit 110 is away from a dominant pole so that the output buffer 100 may ignore influence brought by the node on the entire bandwidth.
Moreover, the compensation capacitor Cc is across-connected with the input terminal of the intermediate-stage unit 120 and an output terminal of the output-stage unit 130. The compensation capacitor Cc is mainly configured for compensation of pole-splitting so that positions of two adjacent poles are split as a low-frequency dominant pole and a position of high frequency capable of ignoring a secondary pole.
Since the output buffer 100 needs the compensation capacitor Cc for the pole-splitting, the compensation capacitor Cc has to be charged or discharged every time when a state of the output terminal of the input-stage unit 110 is changed. Thus, a large signal response speed of the output buffer 100 is determined based on a speed of which the compensation capacitor Cc is charged of discharged by a bias current of the input-stage unit 110. If the compensation capacitor Cc is larger and the bias current of the input-stage unit 110 is smaller, the large signal response speed of the output buffer 100 is the slower. Otherwise, if the compensation capacitor Cc is smaller and the bias current of the input-stage unit 110 is larger, the large signal response speed of the output buffer 100 is faster.
Typically, for maintaining the feature of a normal frequency response, the size of compensation capacitor Cc is fixed once selected. As a result, only the bias current of the input-stage unit 110 is adjustable. In order to increase the large signal response speed of the output buffer 100, the bias current of the input-stage unit 110 has to be designed as larger, which results in increment of entire power consumption of the output buffer 100 and becomes a major issue in this field.